This invention is generally related to techniques for phase aligning two digital clock signals.
The use of a digital clock signal in electronic systems provides an effective and low cost technique to synchronize events, so that the events can repeat at a high rate dictated by the clock signal. For instance, separate parts of a complex integrated circuit (IC) die may be responsible for generating different portions of a multiple bit value. This multi-bit value may need to be repeatedly read, in a very short time interval, as defined by a reference digital clock signal.
To ensure that the multi-bit value is timely available, multiple copies of the reference clock are generated and fed to the different parts of the IC die using a clock distribution network, so that each part of the IC die provides its portion of the multi-bit value in response to a rising edge of its copy of the reference clock. However, at very high clock rates, variations in the IC die manufacturing process, supply voltage, the operating temperature of the IC die and design mismatches can lead to serious misalignment of corresponding edges in the copies of the reference clock (referred to as xe2x80x9cclock skewxe2x80x9d), thereby endangering synchronous operation. The design of a robust clock distribution circuit which can operate reliably at very high clock rates is a challenging task that has become a significant portion of the development cost of large, complex IC dies.
A digital phase aligner, such as one based on a delay locked loop (DLL), can be used to automatically decrease clock skew, by for instance adjusting the binary-weighted delay of a variable-delay line to align each output of a clock distribution network to the clock input of an IC die. However, such a circuit may not be space-efficient, such that it might enjoy only limited use in IC dies and printed wiring boards having large clock distribution networks. Moreover, the conventional phase aligner design may not prove to be a sufficiently versatile macro, thus precluding its easy integration in a wide range of applications (beyond deskewing a clock distribution network.) Finally, the phase aligner may not be sufficiently accurate (achieve low skew and jitter) at high clock frequencies.